RTL Modeling with SystemVerilog for Simulation and Synthesis

This book is both a tutorial and a reference for engineers who use the SystemVerilog Hardware Description Language (HDL) to design ASICs and FPGAs. The book shows how to write SystemVerilog models at the Register Transfer Level (RTL) that simulate and synthesize correctly, with a focus on proper coding styles and best practices.SystemVerilog is the latest generation of the original Verilog language, and adds many important capabilities to efficiently and more accurately model increasingly complex designs. This book reflects the SystemVerilog-2012/2017 standards. This book is for engineers who already know, or who are learning, digital design engineering. The book does not present digital design theory; it shows how to apply that theory to write RTL models that simulate and synthesize correctly. The creator of the original Verilog Language, Phil Moorby says about this book (an excerpt from the book’s Foreword): “Many published textbooks on the design side of SystemVerilog assume that the reader is familiar with Verilog, and simply explain the new extensions. It is time to leave behind the stepping-stones and to teach a single consistent and concise language in a single book, and maybe not even refer to the old ways at all! If you are a designer of digital systems, or a verification engineer searching for bugs in these designs, then SystemVerilog will provide you with significant benefits, and this book is a great place to learn the design aspects of SystemVerilog.”

Table of Contents

Chapter 1 SystemVerilog Simulation and Synthesis

Chapter 2 RTL Modeling Fundamentals

Chapter 3 Net and Variable types

Chapter 4 User-defined Types and Packages

Chapter 5 RTL Expression Operators

Chapter 6 RTL Programming Statements

Chapter 7 Modeling Combinational Logic

Chapter 8 Modeling Sequential Logic

Chapter 9 Modeling Latches and Avoiding Unintentional Latches

Chapter 10 Modeling Communication Buses – Interface Ports

Appendix A Best Practice Coding Guidelines

Appendix B SystemVerilog Reserved Keywords

Appendix C X Optimism and X Pessimism in RTL Models

Appendix D Additional Resources