Artificial Intelligence Hardware Design

In Artificial Intelligence Hardware Design: Challenges and Solutions, distinguished researchers and authors Drs. Albert Chun Chen Liu and Oscar Ming Kin Law deliver a rigorous and practical treatment of the design applications of specific circuits and systems for accelerating neural network processing. Beginning with a discussion and explanation of neural networks and their developmental history, the book goes on to describe parallel architectures, streaming graphs for massive parallel computation, and convolution optimization.

The authors offer readers an illustration of in-memory computation through Georgia Tech’s Neurocube and Stanford’s Tetris accelerator using the Hybrid Memory Cube, as well as near-memory architecture through the embedded eDRAM of the Institute of Computing Technology, the Chinese Academy of Science, and other institutions.

Readers will also find a discussion of 3D neural processing techniques to support multiple layer neural networks, as well as information like:

• A thorough introduction to neural networks and neural network development history, as well as Convolutional Neural Network (CNN) models
• Explorations of various parallel architectures, including the Intel CPU, Nvidia GPU, Google TPU, and Microsoft NPU, emphasizing hardware and software integration for performance improvement
• Discussions of streaming graph for massive parallel computation with the Blaize GSP and Graphcore IPU
• An examination of how to optimize convolution with UCLA Deep Convolutional Neural Network accelerator filter decomposition

Perfect for hardware and software engineers and firmware developers, Artificial Intelligence Hardware Design is an indispensable resource for anyone working with Neural Processing Units in either a hardware or software capacity.

Table of Contents

Chapter 1 Introduction

Chapter 2 Deep Learning

Chapter 3 Parallel Architecture

Chapter 4 Streaming Graph Theory

Chapter 5 Convolution Optimization

Chapter 6 In-Memory Computation

Chapter 7 Near-Memory Architecture

Chapter 8 Network Sparsity

Chapter 9 3D Neural Processing

Appendix A Neural Network Topology

About the Authors

Albert Chun Chen Liu, PhD, is Chief Executive Officer of Kneron. He is Adjunct Associate Professor at National Tsing Hua University, National Chiao Tung University, and National Cheng Kung University. He has published over 15 IEEE papers and is an IEEE Senior Member. He is a recipient of the IBM Problem Solving Award based on the use of the EIP tool suite in 2007 and IEEE TCAS Darlington award in 2021.

Oscar Ming Kin Law, PhD, is the Director of Engineering at Kneron. He works on smart robot development and in-memory architecture for neural networks. He has over twenty years of experience in the semiconductor industry working with CPU, GPU, and mobile design. He has also published over 60 patents in various areas.